1. Field of the Invention
The invention generally relates to controlling WLAN (Wireless Local Area Network) devices connected to a data processing system, and in particular to a data processing system and method for controlling a data transfer to and/or from such a WLAN device.
2. Description of the Related Art
A wireless local area network is a flexible data communications system implemented as an extension to or as an alternative for, a wired LAN. Using radio frequency or infrared technology, WLAN systems transmit and receive data over the air, minimizing the need for wired connections. Thus, WLAN systems combine data connectivity with user mobility.
Today, most WLAN systems use spread spectrum technology, a wide-band radio frequency technique developed for use in reliable and secure communication systems. The spread spectrum technology is designed to trade-off bandwidth efficiency for reliability, integrity and security. Two types of spread spectrum radio systems are frequently used: frequency hopping and direct sequence systems.
The standard defining and governing wireless local area networks that operate in the 2.4 GHz spectrum, is the IEEE 802.11 standard. To allow higher data rate transmissions, the standard was extended to 802.11b that allows data rates of 5.5 and 11 Mbps in the 2.4 GHz spectrum. Further extensions exist.
Controlling a WLAN device usually requires some software running on a particular hardware platform. Such software needs to write data from the host to the device and read data from the device to the host. Thus, the software and the WLAN device need to support some transfer mechanism between the host CPU (Central Processing Unit) memory and the WLAN device. One possible transfer mechanism is the DMA (Direct Memory Access) mechanism.
In present computer systems, one way of relieving the central microprocessing unit of performing repetitive input/output functions is to avoid interrupts and to realize these functions by means of a DMA controller which is a control unit that enables direct memory access. Before the actual input/output process takes place, the processor initializes the DMA controller by writing initialization data to its registers, and the DMA controller is then able to independently perform data transfers between memory and interface. That is, during the phase where the control and address registers are initialized, the controller acts as slave. However, as soon as the controller receives a transfer request and begins data transmission, the controller independently performs bus cycles, i.e. it acts as master and shares the bus with the processor, for memory access.
FIG. 1 depicts a conventional system employing a DMA controller. In this system, the processor 100 is connected to the memory 105, the DMA controller 110 and a device control unit 120 that controls the peripheral device 125. Dependent on the mode of operation of the DMA controller 110, the data transfer between memory 105 and device control unit 120 may be performed directly or indirectly, i.e. by means of a buffer 115. In the direct transfer mode, the DMA controller 110 requires only one bus cycle per data item by addressing the memory 105 via the address bus and at the same time, addressing the interface data registers via a control line (single address mode). In the indirect transfer mode, the DMA controller 110 first performs a read cycle and stores the read data in the buffer 115. In a subsequent write cycle, the DMA controller 110 then transfers the buffered data to the respective target unit. Memory and interface are both addressed via the address bus (dual address mode).
While the DMA mechanism provides a data transfer technique that has many advantages when controlling devices such as WLAN devices, this technique cannot be used under all circumstances. For instance, situations exist where no bus master DMA is available in the WLAN device that is to be controlled.
Thus, the existing techniques suffer from the fact that they are strongly dependent on the used hardware and operating system. For instance, if the hardware and software are designed to use DMA, the architecture is limited to this mechanism. This is likewise true for other memory transfer techniques apart from DMA. Thus, the prior art software is limited to run on the respective specific hardware to use hardware acceleration mechanisms like DMA.